Takayasu Sakurai's Fully-Depleted SOI CMOS Circuits and Technology for PDF

By Takayasu Sakurai

Fully-depleted SOI CMOS Circuits and expertise for Ultralow-Power functions addresses the matter of lowering the provision voltage of traditional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit layout for FD-SOI units at a provide voltage of 1/2 V. the subjects comprise the minimal required wisdom of the fabrication of SOI substrates; FD-SOI units and the newest advancements in gadget and approach applied sciences; and ultralow-voltage circuits, reminiscent of electronic circuits, analog/RF circuits, and DC-DC converters. every one ultra-low-power procedure with regards to units and circuits is absolutely defined utilizing figures to aid realizing.

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Sato, “Epitaxial Layer Transfer by Bond and Etch Back of Porous Si,” Appl. Phys. , Vol. 64, pp. 2108-2110, 1994. 20] M. Bruel, “A New Silicon On Insulator Material Technology,” Electron. , Vol. 31, p. 1201, 1995. 21] I. J. Malik, S. W. Bedell, H. Kirk, M. Korolik, S. Kang, M. I. Current, and F. J. Henley, “Substrate Characterisctics of Nanocleave SOI Wafers,” Ext. Abst. of International Conference on Solid State Devices and Materials, pp. 490-491, 2000. 22] K. Ueda, K. Nii, Y. Wada, I. Takemoto, S.

7) As the gradient of log(ID) vs. VG in the subthreshold region becomes steeper, the drain leakage current (off current) at VG = 0 becomes smaller. In addition, for a given off current, a steeper gradient allows the threshold voltage to be made smaller. Producing high-speed LSIs with a low power dissipation requires the use of MOSFETs with a low threshold voltage and a small off current, which in turn requires a steep gradient. The gradient is expressed as the subthreshold swing, S, which is defined to be the change in gate voltage needed to change the drain current by one decade in the subthreshold region, as shown by the following formula.

18 Ultrathin FD-SOI GeOI G 90-nm node (Lg ~ = 60nm) PD/FD-SOI Bulk-Si MOSFET G D BOX Sub G S S (Lg ~ = 20nm) DELTA FinFET p - FET Ω - FET etc. D BOX Sub G BOX Sub Strained-Si SOI Strained Si Relaxed SiGe BOX Sub Doublegate (DG) MOSFET G G • Lower capacitance •Suppression of short-channel effects • Higher mobility •Ultrathin-film SOI / 3D structure Fig. 18 Evolution of MOSFET structure. 6 Summary After many years of research and development, SOI technology has finally become a reality. Applications range from MPUs and low-power LSIs to RF/mixed-signal and high-voltage circuits.

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